工学院では、著名な講師の方々をお招きして、特別セミナーを開催しています。
今回は、バル・イラン大学（Bar-Ilan University, Israel）のShmuel Wimer名誉教授（本学特任教授）にご講演いただきます。
日時 |
2019年10月26日（土）13:30 - 14:30 |
|---|---|
場所 |
東京工業大学 大岡山キャンパス 本館1階 H114講義室 |
主催 |
東京工業大学 工学院 システムLSI合同ゼミ |
協賛 |
IEEE CASS Japan Joint Chapter, IEEE CEDA All Japan Joint Chapter |
講演概要
Analyses and simulations have shown that interconnect shielding can replace a large fraction of the delay buffers used to achieve timing goals through a useful skew clock design methodology. Immunity from process, operation, and environmental variations in nanoscale CMOS technology clock designs are essential, thus making predictable delays and useful skews highly important. We examine interconnect shielding intra die within-die (WID) and inter die die-to-die (D2D) variations under a wide variety of (P,V,T) corners, and show their applicability and ability to achieve clock design timing goals. The analysis is based on post-silicon measurements of a novel shielded interconnect ring oscillator in a 16-nm test chip supported by a rigorous provable estimation methodology.
講演者の略歴
Emeritus Prof. Shmuel Wimer
Shmuel Wimer is a Professor Emeritus with the Engineering Faculty of Bar-Ilan University, Israel. He received his B.Sc. and M.Sc. degrees in Mathematics from Tel-Aviv University, Israel, in 1978 and 1981, respectively, and his D.Sc. degree in Electrical Engineering from the Technion-Israel Institute of Technology, Israel, in 1988. From 1978 to 2009 he held R&D, engineering and managerial positions in industry. From 1999 to 2009 he was with Intel, and prior to that with IBM, National Semiconductor, and the IAI-Israel Aerospace Industry. Since 2009 he is with Bar-Ilan University. His interests are in VLSI circuits and systems design optimization and combinatorial optimization.